
132
8024A–AVR–04/08
ATmega8HVA/16HVA
23.9.9
BPDHCD – Battery Protection Discharge-High-current Detection Level Register
Bits 7:0 – DHCDL7:0: Discharge High-current Detection Level
These bits sets the R
SENSE voltage level for detection of Discharge High-current, as defined in
Note:
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDHCD register is written. Any
writing to the BPDHCD register during this period will be ignored.
23.9.10
BPCHCD – Battery Protection Charge-High-current Detection Level Register
Bits 7:0 –CHCDL7:0: Charge High-current Detection Level
These bits sets the R
SENSE voltage level for detection of Charge High-current, as defined in
Note:
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCHCD register is written. Any
writing to the BPCHCD register during this period will be ignored.
Bit
765
432
10
DHCDL[7:0]
BPDHCD
Read/Write
R/W
Initial Value
1
0
1
Bit
765
4321
0
CHCDL[7:0]
BPCHCD
Read/Write
R/W
Initial Value
111
1001
1
Table 23-5.
DL[7:0] with corresponding R
SENSE Current for all Current Detection Levels
(R
SENSE = 10 mΩ, VREF = 1.100 ± 0.005V, TA = -10°C to 70°C)
Current Protection Detection Level
DL[7:0]
Min.
Typ.
Max.
0xF3
2.0A
0xF4
2.5A
0xF5
3.0A
0xF6
3.5A
0xF7
4.0A
0xF8
4.5A
0xF9
5.0A
0xFA
5.5A
0xFB
6.0A
0xFC
6.5A
0xFD
7.0A